Hi sorry it is taking me so long to get back to you, have to focus really hard for sustained periods of time.
The Kazan software is a Vulkan compliant userspace library and is primarily a SPIRV compiler, which, unlike “standard” GPU drivers will translate directly from SPIRV to LLVM IR, and from there directly into assembly code on the target machine, using the standard LLVM JIT engine.
Normally because the GPU is totally separate (behind a PCIe interface) all the above has to happen… oh except the compiled assembler and the data has to be serialised and shipped over the PCIe bus to the GPU! Talk about insanely complex!
Jacob is actually designing the SPIRV shader compiler to even be independent of LLVM. So there is no reason, some time down the road, stopping a gcc backend from being added.
And yes, one of our intermediary milestones is to get this working first on x86. It should be clear why: we do not want to be tackling two or more unknowns at once, particularly as the RISCV LLVM engine - even without any hardware acceleration to support 3D - is under active development.
We therefore need a stable base to go from, I explain it in more detail, here
https://groups.google.com/a/groups.riscv.org/forum/?nomobile=true#!topic/isa-dev/JlKZdzS6VtQ
The speed grade of the FPGA does not matter, we do however need absolutely massive ones, or to split across a network of smaller FPGAs.
I am talking to someone who wants to do an open ASIC cell library, using alliance / coriolis2 to do the layout, it may be the case that we first do a 180nm test chip.
The nice thing about cell libraries is that they scale well as long as you don’t go mad eg the 3D FINFETs. Also, coriolis2 is driven from python i.e you divide and conquer by module, using each successive layer to construct the next, block by block, writing a python application to choose what to do at each phase.
We can therefore start at 180nm and quite reasonably expect to be able to reuse most of the layout to do a 40nm or 28nm chip.
The tricky bit will be the DRC (Design Rule Checks). coriolis2 does not have the same sort of checks as Mentor and Synopsis, however there is an online company that can do DRC up to 45nm.
So there is actually a way to do this.
Still have to get a PLL block, and a DDR3/4 PHY, and a USB2 PHY. These are all analog and have to be customised not just to the geometry, they often need to be customised to the Foundry.