I’ve read that DDR4 standard included an optional feature to have CRC on data line and parity check on control line.
It sounds like a semi-ECC for everyone, but too little information can be found online.
My questions are:
- Is this feature usually enabled or disabled on consumer devices(such as Purism laptop)?
- How to check it?
- Will it give a log when errors are found(similar to ECC’s behavior)?
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My understanding is it is a more passive behaviour in that it is always on and is simply a means for identifying and flipping back a bit if a bit flips due to the combination of higher speeds and lower voltage as compared to DDR3. When I was first hearing about this several years ago, it was something that each memory chip would have built into it and in turn it wouldn’t even be aware of the memory on another chip on the same dimm.
I don’t know for certain, but I believe the only way to confirm this would be to X-ray the memory chip to show the circuitry is there.
To the best of my knowledge this feature is about real time fixing of errors and not about tracking how often it happens to diagnose a failed/failing DIMM and in turn I don’t believe there are any logs (it’s not impossible, just highly improbable). The goal of this function wasn’t to make ECC for everyone (they sell ECC DDR4 RAM) but rather to solve a problem that comes up where sometimes a few extra electrons end up on the wrong side of the gate and instead of slowing things down it was decided to introduce this quick verification step to make sure all the bits have the correct state before moving on to the next byte (or maybe block, it’s been a while)
Hopefully that helps some.
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