Nlnet Foundation is listing a very interesting and promising project which it is currently funding: NLnet; Flashkeeper
Flashkeeper
Write Protection on SOIC-8 flash chips without soldering
The proposed device would be an easy way to have WP (SPI flash chip Write Protection) grounded, but without having to do any soldering on the MBD, a hazardous endeavor…
But even more ambitious:
For users concerned with physical attacks on their systems, for whom easy access to SPI flash pins may be seen as a risk, a variant including a microcontroller (MCU) is also being developed, allowing authenticated external reprogramming and WP control, and independently verifying the SPI flash image against a user-controlled signature each boot.
Awesome! If they can do such a thing, it means we will have a solution for the weakness of SRTM (measured boot) vs DRTM (hardware-based root of trust such as BootGuard) implementation. The problem being that the root-of-trust is software-based, coreboot’s bootblock
(at reset vector) is hashing itself and other things like FMAP
and then hashes the next stage romstage
before execution; therefore it is the verifier that verifies itself and it can lie about TPM measurements if tampered.
Many people claim that BootGuard is safer, because the root of trust is based in the CPU hardware, ME verifying ACM (unfortunately with Intel’s key) and IBBs (signed bootblocks) before doing the reset vector and start the proper boot sequence.
As I understand it, the Flashkeeper variant would be an MCU (independent hardware) verifying the SPI flash content at each boot - therefore rendering any modification to the image impossible.
We can call this a hardware root-of-trust, or am I wrong?
To be noted: Insurgo (Thierry Laurion) is also involved in this project