What's The Long-Term Proper Fix For Meltdown / Spectre?

I haven’t really read much about anything but software fixes for the issue - which are noted to cause a performance drop.

Has there been any talk that newly made chips won’t have these issues? Will it be gone at least post-Coffeelake (the next generation onwards)? Or is this an issue that’s not feasibly fixable hardware-level and they’re not going to?

I know I’ve heard of stuff like security flaws in RAM that are over a decade old and most manufacturers just NEVER fixed them because it was too much of a hassle - sorta just swept it under the rug.

I know that there is / going to be software fixes/precautions added, but do they intend to actually fix the root problem directly for future processors, or are they just going to use software-side fixes as a crutch, hide behind PR talk, and hope people just forget about it?

I mean, my understanding is that this issue only came to be in the first place because of unethical approaches chip manufactures used to make faster chips without considering security. If this whole problem arose due to unethical practices then I imagine it’d be silly to think they’ll do the ethical thing and fix it now.

But I just wanted to know if there’s any real talk of fixing the real problem physically.

Just thought I’d bring this thought up.

Just replying to add that the memory exploit I mentioned that was on the tip of my tongue is ROWHAMMER. Just forgot the name for a while there, brainfart. Reddit thread that reminded me of it.

That’s still an example of a hardware issue that was largely ignored for years and even now you have to get “LPDDR4” specifically and ensure it’s configured correctly as it’s apparently optional.

I’m worried Meltdown/Spectre will just be the same deal where it goes ignored for ages and the only hardware-level fixes are going to be obscure.

I do hope Purism is using this LPDDR4. I only see “DDR4” on the schematics. Apparently it needs to be this LPDDR4 because only it does “Target Row Refresh” which is the rowhammer mitigation method. All in all you need to enable this “TRR” thing somehow and I do hope Purism knows this and has done so.

I know it may be a bit ridiculous, but I do hope there’s ECC memory that supports hardware TRR as well. That’d be perfect.

I’m not going to pretend I know what all this is, I’m just hoping this isn’t something old that slipped consideration. Definitely something you may want to put in Revision 4 if you haven’t already.